CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 1 document title 512k x 16 bit super low power and low voltage full cmos ram revision history final dec. 15 th , 2006 removed vccq related information & typo. 0.4 final sep. 6 th , 2006 added power up sequence 0.3 final apr. 06 th , 2007 added ?rohs compliant? descriptions 0.5 final aug. 21 st , 2006 removed 60ns part 0.2 final aug. 16 th , 2006 corrected timing diagrams & functions (about cs2) 0.1 final jul. 04 th , 2006 initial draft 0.0 remark draft date history revision no.
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 2 512k x 16 bit super lo w power and low volt age full cmos ram pin description no connection nc core power vcc chip select input /cs lower byte(i/o 1~8) /lb data inputs/outputs i/o1~i/o16 upper byte(i/o9~16) /ub address inputs a0~a18 ground vss write enable input /we output enable input /oe function name function name features ? process technology : full cmos ? organization : 512k x 16 ? power supply voltage : 2.7~3.6v ? three state output and ttl compatible ? package type : 44-tsopii (400f) ? automatic power-down when deselected ? CMP0817BA0-P70I is rohs compliant product family isb1 (cmos standby current) icc2 icc1 max. typ. 20ma max. typ. max. typ. min. 70ua 3.0 typ. max. 30ua 12ma 3ma 1.5ma 70ns 3.6 2.7 industrial (-40~85?c) cmp0817ba0- p 70i operating voltage (v) f = fmax f = 1mhz power dissipation speed operating temperature product family functional block diagram precharge circuit. clk gen. vcc vss memory array row addresses i/o circuit column select data cont data cont column addresses data cont control logic /cs /oe /we /ub /lb i/o9~i/o16 i/o1~i/o8 row select 1. typical values are included for reference only and are not guar anteed or tested. typical values are measured at vcc = vcc ( typ) and t a = 25c. 2. . t =tsop, p =tsop (pb-free), w =wafer 44-pin tsop-ii : top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a4 a3 a2 a1 a0 /cs i/o1 i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 /we a18 a17 a16 a15 a14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 a7 /oe /ub /lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 a8 a9 a10 a11 a12 a13 CMP0817BA0-P70I 44-pin tsopii
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 3 product list 44-tsopii, 70ns, vcc=3.0v cmp0817ba0- p 70i function part name industrial temperature products(-40~85?c) functional description absolute maximum ratings 1) ?c -40 to 85 t a operating temperature ?c -65 to 150 t stg storage temperature w 1.0 p d power dissipation v -0.2 to 3.6 vcc voltage on vcc supply relative to vss v -0.2 to vcc+0.3v v in , v out voltage on any pin relative to vss unit ratings symbol item 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for industria lperiods may affect reliability. recommended dc operating conditions 1) -0.2 3) 0.8vcc 0 2.7 min cmp0817ba0 0.2vcc vcc+0.2 2) 0 3.6 max v v cc supply voltage v v il input low voltage v v ih input high voltage v v ss ground unit symbol item note : 1.t a =-40 to 85?c, otherwise specified. 2. overshoot : vcc+1.0v in case of pulse width 20ns. 3. undershoot : -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. 1. t =tsop, p =tsop (pb-free), w =wafer active word write din din l l active upper byte write din high-z l h active lower byte write high-z din h l l x 1) active word read dout dout l l active upper byte read dout high-z l h active lower byte read high-z dout h l h l l active output disabled high-z high-z l x 1) h h active output disabled high-z high-z x 1) l h h l standby deselect/power-down high-z high-z h h x 1) x 1) x 1) standby deselect/power-down high-z high-z x 1) x 1) x 1) x 1) h power mode i/o9-16 i/o1-8 /ub /lb /we /oe /cs 1. x means don?t care.(must be low or high state)
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 4 dc and operating characteristics 1. capacitance is sampled, not 100% tested. capacitance 1) (f=1mhz , t a =25?c) 8 8 max - - min pf v io =0v c io input/output capacitance pf v in =0v c in input capacitance unit test condition symbol item ua 70 - - /cs v cc -0.2v, other inputs=0~v cc i sb1 standby current(cmos) ua 1 - -1 /cs=v ih , /oe=v ih or /we=v il , v io =v ss to v cc i lo output leakage current ua 1 - -1 v in =v ss to v cc i li input leakage current ma 3 1.5 - cycle time=1us, 100%duty, i io =0ma, /cs 0.2v, v in 0.2v or v in v cc -0.2v i cc1 average operating current v 0.2vcc i ol =0.5ma v ol output low voltage ma 25 15 - cycle time=min, i io =0ma, 100% duty, /cs=v il , v in =v il or v ih i cc2 v 0.8vcc i oh =-0.5ma v oh output high voltage 0.3 max - typ - min ma /cs=v ih , other inputs=v ih or v il i sb standby current(ttl) unit test conditions symbol item
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 5 ac operating conditions test conditions (test load and input/output reference) input pulse level : 0.2 to vcc-0.2v input rising and falling time : 5ns input and output reference voltage : 0.5*vcc output load(see right) : c l =30pf+1ttl ac characteristics (v cc =2.7v~3.6v, industrial product : t a =-40 to 85?c) 30pf 1ttl ns - 10 tcp /cs high pulse width 1) ns - 5 tow end write to output low-z ns - 0 tdh data hold from write time ns - 20 tdw data to write time overlap ns 5 0 twhz write to output high-z ns - 0 twr write recovery time ns - 50 twp write pulse width ns - 60 tbw /ub, /lb valid to end of write ns - 60 taw address valid to end of write ns - 0 tas address set-up time ns - 60 tcw chip select to end of write ns 80k 70 twc write cycle time write ns - 5 toh output hold from address change ns 5 0 tohz output disable to high- z output ns 5 0 tbhz /ub, /lb disable to high- z output ns 5 0 thz chip disable to high- z output ns - 5 tolz output enable to low-z output 70ns ns - 10 tblz /ub, /lb enable to low-z output ns - 10 tlz chip select to low-z output ns 70 - tba /ub, /lb access time ns 25 - toe output enable to valid output ns 70 - tco chip select to output ns 70 - taa address access time ns 80k 70 trc read cycle time read max min units symbol parameter list 1. /cs high pulse width is defined by /cs or (/ub and /lb) because /ub & /lb can make standby mode when /ub=high and /lb=high.
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 6 power up sequence 1. apply power 2. maintain stable power for a minimum of 200us with /cs=v ih standby mode state machines standby mode characteristics initial state standby mode active mode power on /cs=v ill /cs=v ih (or/and /ub=/lb=v ih ) /cs=v ih /cs=v il , /ub or/and /lb=v il 0 70 (isb1) valid standby mode memory cell data wait time(us) standby current(ua) wait min.200us
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 7 read cycle (1) (address controlled,/cs=/oe=v il , /ub or/and /lb=v il ) address data out trc previous data valid data valid taa toh read cycle (2) (/we=v ih ) 1. thz and tohz are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing s horter than trc(twc) for continuous periods > 80us. address taa tco tba toe toh tolz tblz tlz data valid high-z thz tbhz tohz /cs /ub, /lb /oe data out trc
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 8 write cycle (2) (/cs controlled, /we=v ih ) address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) tas(3) taw write cycle (3) (/ub, /lb controlled) 1. a write occurs during the overlap (twp) of lo w /cs and /we. a write begins when /cs goes low and /we goes low with asserting /ub or /lb for single byte operation or simultaneou sly asserting /ub and /lb for double byte operation. a write ends at the earliest transition when /cs goes high and we goes high. the twp is measured from the beginning of write to the end of write. 2. tcw is measured from the /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. do not access device with cycle timing s horter than trc(twc) for continuous periods > 80us. address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) taw tas(3) write cycle (1) (/we controlled) address /cs /ub, /lb /we data out twc tcw(2) twr(4) taw tbw twp(1) tas(3) high-z high-z data undefined data valid tdw tdh tow twhz data in
CMP0817BA0-P70I cmos lpram revision 0.5 apr. 2007 9 package dimension 44 pin thin small outline package type ii (400f) unit : millimeters
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